1. Field of the Invention
The present invention relates to semiconductor memory devices and methods of manufacturing the same. More particularly, embodiments of the present invention relate to flash memory devices including floating gates and methods of manufacturing the same.
2. Description of the Related Art
Semiconductor memory devices are divided into volatile memory devices and nonvolatile memory devices. Volatile memory devices, such as dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices, lose data when supply power is interrupted. However, an input/output speed of data for such devices is fast. Non-volatile memory devices, such as read only memory (ROM) devices, do not lose data when supply power is interrupted. However, the input/output speed of data in such devices is relatively slow. Among the ROM devices, electrically erasable and programmable read only memory (EEPROM) devices, particularly, flash memory devices have been used widely.
A unit cell of a flash memory device has a gate structure including a floating gate. In particular, the gate structure of the flash memory device has a stacked structure in which a floating gate, a dielectric layer and a control gate are sequentially stacked on a tunnel insulation layer.
Examples of methods of manufacturing flash memory devices are disclosed in Korean Laid-Open Patent Publication No. 2004-005230, U.S. Pat. No. 6,743,675, etc. A method of manufacturing a flash memory device disclosed in the above documents is illustrated with reference to FIGS. 1A to 1I.
Referring to FIG. 1A, a pad oxide layer 110 and a pad nitride layer 120 are formed on a substrate 100.
Referring to FIG. 1B, an upper portion of the substrate 100 is partially etched using the pad nitride layer 120 and the pad oxide layer 110 as an etching mask, so that a trench 105 is formed to divide the substrate 100 into an active region and a field region.
Referring to FIG. 1C, an isolation layer 130 is formed on the substrate 100, the pad oxide layer 110 and the pad nitride layer 120 to fill up the trench 105 using undoped silicate glass (USG) oxide or high-density plasma (HDP) oxide.
Referring to FIG. 1D, the pad nitride layer 120 is removed by a stripping process, and the pad oxide layer 110 is removed by a wet etching process, thereby forming an opening 135 partially exposing the substrate 100. The stripping process and the wet etching process are performed in an isotropic direction using phosphoric acid solution and fluoride acid solution, respectively. During the stripping process and the wet etching process, a portion of the isolation layer 130 is also removed, so that the opening 135 has a peripheral portion having a depth greater than that of a central portion thereof.
Referring to FIG. 1E, a tunnel insulation layer 140 is formed on the active region of the substrate 100 exposed by the opening 135. Additionally, a floating gate layer 150 is formed on the tunnel insulation layer 140, a sidewall of the opening 135 and the isolation layer 130 using polysilicon. A sacrificial layer 170 is formed on the floating gate layer 150 using USG oxide to fill up the opening 135.
Referring to FIG. 1F, an upper portion of the sacrificial layer 170 and an upper portion of the floating gate layer 150 are removed to expose the isolation layer 130. Thus, the sacrificial layer 170 and the floating gate layer 150 are transformed into a sacrificial layer pattern 172 and a preliminary floating gate 152, respectively.
Referring to FIG. 1G, an upper portion of the preliminary floating gate 152 are removed by an anisotropic etching process to form a floating gate 154. The floating gate 154 is formed to have a peripheral portion having a thickness greater than that of a central portion thereof.
Referring to FIG. 1H, the sacrificial layer pattern 172 is removed, and an upper portion of the isolation layer 130 is removed so that the isolation layer 130 has a height substantially the same as that of the peripheral portion of the floating gate 154.
Referring to FIG. 1I, a dielectric layer 180 and a control gate 190 are formed on the floating gate 154 and the isolation layer 130, thereby forming the flash memory device.
In the method of manufacturing a flash memory device described above, when the pad nitride layer 120 and the pad oxide layer 110 are removed, the opening 135 has a peripheral portion having a depth greater than that of the central portion thereof. Thus, in the case of the floating gate 154 that is formed by partially removing the floating gate layer 150 on the active region of the substrate 100 exposed by the opening 135, the peripheral portion thereof has a thickness greater than that of the central portion thereof, and thus the floating gate 154 may not have a uniform thickness. Due to the non-uniformity of the thickness of the floating gate 154, the floating gate coupling between adjacent floating gates 154 on neighboring bit lines may not be uniform, and thus a unit cell of the flash memory device including the floating gate 154 may not have uniform operating characteristics.